The present invention relates to the field of integrated circuitry, and, more particularly, to integrated circuits including a clock circuit connected to a secondary circuit, the two circuits being in respectively different power supply domains.
The integrated circuit of the invention has been specifically been designed for use in situations where a first battery powers the clock Circuit and a second battery powers the secondary circuit, and will be described hereinafter with reference to this specific embodiment. However, it will be appreciated that the invention may be applied to a number of different scenarios.
It is often desirable to power a clock circuit independently of another secondary circuit. A typical example is a camera, where the main battery that powers the shutter release and wind-on motor for film drains quickly and needs to be replaced relatively often. To prevent loss of clock and other data settings when the main battery goes flat, it is customary to provide a clock battery that powers only the clock part of the circuitry. Given that most modern clock circuits are of CMOS construction, they tend to be relatively energy efficient, and can run for long periods of time powered only by a small battery such as a xe2x80x9cbuttonxe2x80x9d type battery. An example of this split power domain arrangement is illustrated in FIG. 1.
Whilst this arrangement is useful when the device is in operation, it raises some difficulties due to the behaviour of the circuitry when the main battery fails. For example, it is usual to configure devices such that the clock data maintained by the clock circuitry can be amended or updated via other circuitry powered by the main battery. Unfortunately, the control paths used to effect is can be the cause of spurious signals as the main battery fails, which in certain combinations at particular times can cause the clock data to inadvertently be changed.
Typically, during operation, the power supply to the secondary circuit is monitored, and whenever it drops outside of an acceptable range, a reset signal is given to the device. This reset signal causes all flip-flops within the device (ie, excluding the clock circuit) to be reset. Since this signal is always active whenever the main chip is powered down, it can be used by the clock circuit to determine whether control signals attempting to change the clock data within the clock circuit are valid. One way of using the reset signal is to include a comparator that prevents updating of the clock data when the secondary circuit is powered down.
Unfortunately, the introduction of such a component can reduce testability, or at least speed of testing, of the circuitry during manufacture. During such testing, Automatic Test Pattern Generation (ATPG) creates patterns of stimuli that are applied to the circuit to ensure that every single gate and wire is tested. However, some signals are considered special in the ATPG process, clock and system reset being examples.
Because the reset signal is used as a reset for the rest of the chip, the circuitry that implements the corruption protection cannot be tested at the same time as the rest of the chip, because the ATPG process requires the value of the signal to change. This will cause major problem with the rest of the chip, as any test pattern will be overridden by the reset signal. This means that the clock corruption protection circuitry must be tested on its own rather than in parallel with the rest of the chip, thereby lengthening the total time taken to test a device.
It is an object of the invention to provide circuitry that prevents spurious signals from inappropriately amending real-time clock data within a clock circuit as a connected circuit is powered down or reset, whilst improving testability over prior art arrangements.
The present invention provides integrated circuitry including a clock circuit powered by a first power supply and a secondary circuit powered by a second power supply, the secondary circuit including:
a control signal output for supplying a control signal to the clock circuit; and
a clock data output for outputting new clock data to the clock circuit;
the clock circuit including.
clock generation means for generating current clock data and outputting it to the secondary circuit;
detection means for monitoring voltage from the second power supply and generating a system reset signal for supply to the secondary circuit in the e-vent the voltage falls below a predetermined level;
a first latch having a reset operable by a predetermined state of the system reset output generated by the detection means;
a comparator accepting as inputs the control signal from the secondary circuit and an output of the first latch; and
a multiplexor accepting as data inputs the clock data from the secondary circuit and the clock data from the clock circuit, and accepting as a control input the output of the comparator;
the integrated circuitry being configured such that:
when the secondary circuit is not asserted and the control signal is asserted, the current clock data in the clock circuit is replaced with the new clock data; and
when the first latch is reset, the comparator and multiplexor prevent current clock data from being replaced by data from the secondary circuit.
In a preferred form, the first latch is a D-type latch accepting as an input a logical high. More preferably, the input of the D-type latch is tied to the first power supply.
Preferably, the output of the multiplexor is latched by a second latch.